1. Field of the Invention
This invention relates to integrated circuit devices and more particularly to deep trench capacitors and methods of manufacture thereof.
2. Description of Related Art
Currently, Deep Trench (DT) capacitor technology suffers from several problems which limit scalability. Some of those problems are listed as follows:
(1) the excessive resistance of the DT fill which forms the inner capacitor plate reduces the effectiveness of the DT capacitor;
(2) the adverse effect of the work function of the DT fill of the inner capacitor node electrode on the reliability of the node dielectric;
(3) the vertical parasitic (non-scalability of the thickness of the isolation collar oxide effects the choice of DT fill work function and DT operating biases on vertical parasitic).
In the past, problems of resistance of DT fill have been dealt with without regard to other deep trench capacitor scaling problems. In such cases one solution proposed was to solve to the deep trench resistance problem, without seeking a reduction in the thickness of the collar oxide at a time frame when increasing the collar thickness was not a concern because the minimum feature size used was sufficiently large.
An object of this invention is to provide an improved DT capacitor structure, and methods for fabrication, which reduces capacitor electrode series resistance.
Another object of this invention is to provide an improved DT capacitor structure, and methods for fabrication, which minimizes the electric field stress for the node dielectric.
Still another object of this invention is to provide an improved DT capacitor structure, and methods for fabrication, which allows thinner collar isolation oxide without degrading the vertical parasitic Vt.
Another object of this invention is to provide an effective capacitor node work function which closely matches the work function of the buried, outer electrode (plate electrode), thereby allowing a level of plate bias voltage which will minimize electrical stress on the node dielectric layer between the outer electrode and the inner electrode, also referred to as the storage node or the node conductor, of the capacitor without degrading the vertical parasitic threshold voltage VT.
This invention provides an integrated solution to deep trench capacitor scaling. This integrated solution addresses not only the deep trench resistance problem, but also seeks an integrated solution for allowing thinner collar and minimizing node dielectric stress.
In accordance with this invention, a device and method of forming the device comprising a deep trench capacitor is provided. An open top deep trench if formed with sidewalls and a bottom formed in a semiconductor substrate which is doped with a dopant of a first polarity by the following steps. Form an isolation collar recessed below the top and spaced away from the bottom, composed of a thin film of a dielectric material with confronting sides of the isolation collar formed along the sidewalls of the trench in a space intermediate the top and the bottom of the deep trench. Form a plate electrode region of the substrate surrounding the trench below the isolation collar by counterdoping the plate electrode region through the sidewalls and the bottom with a dopant of the opposite polarity. Form a node dielectric for the capacitor therewith on the exposed sidewalls and exposed bottom of the deep trench thereby covering exposed surfaces of the plate electrode. Form a buffer on the surface of the node dielectric comprising polysilicon doped with a dopant of the opposite polarity. Form a conductive lower diffusion barrier layer over the buffer. Form a bulk inner electrode on the surface of the lower diffusion barrier layer the bulk inner electrode being composed of polysilicon which is doped with a dopant of first polarity. Form a conductive upper diffusion barrier layer over the bulk inner electrode reaching between confronting sides of the isolation collar. Form a polysilicon cap on the surface of the conductive upper diffusion barrier layer with a strap formed on the periphery thereof the polysilicon cap being doped with a dopant of the opposite polarity. Form a strap region by diffusion of dopant of the opposite polarity into a region in the substrate juxtaposed with the periphery of the polysilicon cap. The buffer layer composed of polysilicon doped with a dopant matching the polarity of the outer electrode provides a work function which closely matches the work function of the outer electrode thereby allowing a plate bias of 0.75V with a zero to 1.5V swing on the bulk inner electrode for minimized stress on the node dielectric layer without degrading the vertical parasitic threshold voltage VT.
Preferably, the substrate comprises a doped silicon chip and the buffer region the bulk inner electrode and the cap all comprise doped polysilicon Preferably, the substrate comprises a doped silicon chip and the buffer region the plate electrode and the cap all comprise doped polysilicon and
Preferably, each of the lower and upper diffusion barrier layer are composed of a material selected from the group consisting of TiN and WN.
Preferably, the substrate comprises a doped silicon chip and the buffer region the bulk inner electrode and the cap all comprise doped polysilicon. Form each of the lower and upper diffusion barrier layers of a material selected from the group consisting of TiN and WN. Form a blanket thin film of the upper diffusion barrier covering the node conductor and the upper portion of the isolation collar. Form a silicon oxide layer on the horizontal surfaces of the upper diffusion barrier including the portion above the bulk inner electrode, and etch away the vertical surfaces of the upper diffusion layer. Form the silicon oxide layer by a method selected from the group consisting of the step of a) Form HDP oxide in an anisotropic deposition of a horizontal layer, and b) Form a recessed mandrel above the upper diffusion barrier.
Preferably, the substrate comprises a doped silicon chip and the buffer region the bulk inner electrode and the cap all comprise doped polysilicon. Form each of the lower and upper diffusion barrier layers of a material selected from the group consisting of TiN and WN. Form a blanket thin film of the upper diffusion barrier covering the bulk inner electrode and the upper portion of the isolation collar. Form a silicon oxide layer on the horizontal surfaces of the upper diffusion barrier including the portion above the bulk inner electrode. Etch away the vertical surfaces of the upper diffusion layer. Form the cap on the surface of the upper diffusion layer.
Preferably, the substrate comprises a doped silicon chip and the buffer region the bulk inner electrode and the cap all comprise doped polysilicon. Form each of the lower and upper diffusion barrier layers of a material selected from the group consisting of TiN and WN. Form a blanket thin film of the upper diffusion barrier covering the bulk inner electrode and the upper portion of the isolation collar. Form a silicon oxide layer on the horizontal surfaces of the upper diffusion barrier including the portion above the bulk inner electrode. Etch away the vertical surfaces of the upper diffusion layer. Form a very thin layer of silicon nitride on the exposed surfaces of the sidewalls. Form the cap on the surface of the upper diffusion layer in contact with the very thin layer of silicon nitride. Form pad mask over the substrate with an opening for etching the trench. Form the trench etching through the opening. Form the isolation collar to the top of the pad mask.
In accordance with another aspect of the invention, form a pad mask over the substrate with an opening for etching the trench. Form the trench by etching through the opening. Form the isolation collar to the top of the substrate. Form the buffer region and the lower diffusion layer; form the bulk inner electrode and recess the plate electrode. Form sidewall spacers alongside the isolation collar above the bulk inner electrode; form the upper diffusion barrier as a blanket layer; mask the horizontal surfaces of the upper diffusion barrier and etch away the vertical part of the upper diffusion barrier; and strip away the sidewall spacers. Deposit and recess the cap; and etch away exposed portions of the upper diffusion barrier.
Preferably, form the capacitor in a P-well; form the plate by doping with N+ dopant; form the buffer region as a thin layer of polysilicon doped with N+ dopant form the node conductor of the polysilicon doped with P type dopant and layer, and form the cap of the N+ doped polysilicon.